Today, the NanoIC pilot line, a European initiative coordinated by imec and dedicated to accelerating innovation in chip technologies beyond 2 nm, releases two first-of-a-kind advanced interconnect process design kits (PDKs): a fine-pitch redistribution layer (RDL) and die-to-wafer (D2W) hybrid bonding PDK. These early-access PDKs bring advanced packaging capabilities within reach of universities, start‑ups, and industry innovators and mark an important step in enabling high‑density, energy‑efficient chip‑to‑chip connectivity.

As the semiconductor industry moves toward ever more complex and heterogeneous system architectures, advanced packaging has become a key enabler in supporting this progress. Instead of merely enclosing individual chips, today's packaging technologies bring multiple dies (chiplets) together into tightly integrated systems where performance, energy efficiency, and bandwidth hinge on how effectively those components can interact. By enabling chiplets to be interconnected at high density, advanced packaging provides the foundation for the next generation of high‑performance computing, AI accelerators, and data‑intensive applications.