Samsung is overhauling the power delivery network in its HBM4E memory to tackle what's becoming one of the bigger engineering headaches in next-gen AI chips. This comes just two weeks after the company shipped its first commercial HBM4 , already pushing 11.7 Gbps consistently with headroom up to 13 Gbps. As designs move from HBM4 to HBM4E, the number of power bumps grows from 13,682 to 14,457, packed into the same space with thinner, denser wiring. That drives up current density and resistance, causing IR drop (voltage weakens as it travels through the circuits) while the heat generated in the process makes things worse, creating a feedback loop that can affect performance or even cause circuit failure.

To fix this, Samsung segmented the power network. The large centralized MET4 power block on the base die, previously laid out in big honeycomb-like sections near the interposer, has been split into four smaller sections, with upper layers further broken up to reduce congestion and shorten routing paths. According to Samsung, the results were significant, metal circuit defects dropped 97% compared to HBM4 , and IR drop improved by 41%, giving the chip more voltage headroom for higher speeds and better reliability.