TSMC updates roadmap through 2029 with A13, A12, N2U and bigger CoWoS
© TSMC TSMC has introduced its A13 process at the 2026 North America Technology Symposium in Santa Clara. The company describes A13 as a direct shrink of A14, with 6% area savings, full design-rule backward compatibility, and added power and performance gains through design-technology co-optimization. A13 is scheduled to enter production in 2029, one year after A14.
TSMC previewed A12 as an A14 platform enhancement with Super Power Rail backside power delivery for AI and HPC designs, also targeting 2029 production. N2U was announced as another extension of the 2nm family, with TSMC claiming 3% to 4% higher speed or 8% to 10% lower power than N2P, plus a 1.02x to 1.03x logic density gain, with production set for 2028.
Unveiled at the event
- TSMC is also previewing its A14 platform enhancement A12 , which features Super Power Rail technology to provide backside power delivery for AI and HPC applications. A12 is also scheduled to enter production in 2029.
- TSMC continues to advance its 2nm platform with the introduction of N2U , which employs design-technology co-optimization to reach speed gains of 3-4% or power reduction of 8-10% and a 1.02-1.03X logic density improvement from N2P. A balanced option for AI, HPC, and mobile applications leveraging the process maturity and strong yield performance of the 2nm technology platform, N2U is scheduled for production in 2028.
TSMC says it is already producing 5.5-reticle CoWoS and plans to bring a 14-reticle version to production in 2028, enough to integrate about 10 large compute dies and 20 HBM stacks. The company also expects to move beyond 14 reticles in 2029, alongside its 40-reticle SoW-X platform, while A14-to-A14 SoIC stacking is also planned for 2029 with 1.8x higher die-to-die I/O density than N2-on-N2 SoIC.
© TSMC TSMC also outlined updates for optics, automotive, and specialty processes. Its COUPE co-packaged optics solution on substrate is scheduled to begin production in 2026, and TSMC says it can deliver 2x better power efficiency and 10x lower latency than a pluggable board-level design. For automotive chips, TSMC announced N2A as its first automotive-grade nanosheet process, with 15% to 20% speed gains over N3A at the same power and AEC-Q100 qualification targeted for 2028. The company also said N16HV enters production in 2026 for display driver applications.
Source: TSMC
