According to the latest research from Morgan Stanley, one of the leading investment banks, we have learned that the defect rate for Intel's 14A node is currently reported at D0=0.5. This means that defects in Intel's 14A node production are occurring at a rate of only 0.5, indicating a limited amount of purely non-functional silicon produced during the long and challenging semiconductor manufacturing process. For Intel, this suggests that the 14A node is still in the early stages of ramping up. However, the previous claims that this node is currently surpassing the 18A node at a similar development and ramp time are indeed accurate. For example, Intel plans to target a defect rate of only 0.1 to 0.2 by the first quarter of 2027, when the company intends to start running internal test chips and initiate a slight ramp-up for its own products. This will be followed by risk production in 2028 and high-volume production in 2029.

Looking at Intel's current "Panther Lake" SoC, which integrates multiple smaller dies into a unified package, we observe that Intel has utilized its 18A node for the compute tile's production. This tile measures approximately 8.004 x 14.288 mm, resulting in a silicon area of 114.304 mm². If we take this die size and apply the current parameters of the 14A node, we can estimate that a similar die, with the same surface area but increased density and manufactured on the 14A node, would achieve a yield of 56.45% for designs of that scale. Naturally, the current 18A node is providing better yields due to high-volume manufacturing, but the initial statistics for 14A appear promising. This assumption is based on a die of that specific size, with that particular defect rate, using High-NA EUV half-field exposures in the production process. We believe this is the stage Intel's 14A node is currently at, with room for many improvements. While Morgan Stanley notes in their report that the yield is about 40% for a test chip, its size must be significantly larger than the assumed size of the "Panther Lake" compute tile.