Yesterday, Qualcomm announced its High Bandwidth Compute (HBC) product, a memory-compute solution hybrid designed to replace traditional High Bandwidth Memory (HBM) and offer greater performance, efficiency, and throughput. HBC utilizes LPDDR memory, stacking them across multiple layers in a 3D vertical space and interconnecting them with through-silicon vias (TSVs). This approach provides better energy efficiency than traditional HBM, which stacks regular DDR in vertical layers, as the low-power DDR (LPDDR) chips consume less power while delivering similar bandwidth and capacity. Qualcomm has successfully stacked multiple LPDDR layers on top of each other, with the base of the HBC being a compute die that performs near-memory computation and offloads some processing from the main processor.

This technique is similar to what HBM4 memory currently does, with the base die being a logic die to better integrate compute solutions underneath for packet tracing and data preparation for entering and exiting HBM. However, Qualcomm aims to achieve higher efficiency and more optimized data movement, with a 6x increase in bandwidth per watt compared to the current HBM specification, likely HBM4. HBC Gen 1 achieved 133 TB/s of bandwidth on the AI250 accelerator, a 18x increase over the LPDDR5X currently used in the AI200 card from Qualcomm. The company also claims there is a viable roadmap for using HBC across many Qualcomm AI accelerators, with HBC Gen 1 shipping with the AI250 AI accelerator in mid-2027. The next-generation HBC Gen 2 is expected to yield further significant gains in bandwidth.