Intel updated their ISA programming reference manual and the newly-published version now eliminates AMX-TF32 as well as User-Timer Events and Interrupts. AMX-TF32 was the planned ISA extension for adding the NVIDIA TensorFloat-32 "TF32" format natively to Advanced Matrix Extensions (AMX). TF32 allows the range of FP32 but with the performance of FP16 for AI/matrix computations.
Intel documentation introduced AMX-TF32 in 2024 and the Diamond Rapids compiler patch confirmed AMX-TF32 as an ISA capability of those next-gen Xeon P-core processors.
Diamond Rapids processors are expected to launch in 2027 while now AMX-TF32 is being stripped away as a late change.
The updated ISA documentation drops the AMX-TF32 as well as User-Timer Events and Interrupts. This patch from Intel today goes ahead and removes AMX-TF32 from the GCC compiler. The support is being stripped away given " no actual hardware " is availablr with this functionality. It's also dropping AMX-TF32 from the Diamond Rapids target. As Diamond Rapids appeared in GCC 15 and GCC 16 with AMX-TF32 support included, back-ported patches are now needed to remove that feature.
AMX-TF32 now shares a similar fate of AMX-TRANSPOSE that was killed last year and also slated to be an AMX feature of Diamond Rapids.