AMD Instinct MI200 with 110 Compute Units?

ROCm update might have revealed the configuration of the MI200 accelerator.

Coelacanth’s Dream spotted a Github commit indicating a possible configuration of the upcoming AMD accelerator based on the Aldebaran processor. This GPU is to feature CDNA2 architecture and it is believed to carry an internal codename of GFX90A, indicating it is a derivative of GFX 9th Family (Vega) architecture.

The code lists GFX906_60 which is assumed to be Instinct MI60, GFX908_120 which is Instinct MI100, and GFX90A_110, more than likely being the next-gen flagship accelerator from AMD. The GFX numbers are not important here, but the numbers attached to those GPU architecture IDs are. The 60 stands for 60 Compute Units, a configuration of MI60, while 120 stands for 120 Compute Units for Instinct MI100. The 110 would therefore be a configuration of MI200. Thus, the graphics accelerator would feature 110 Compute Units, 10 fewer than Arcturus.

ROCm commit with GFX90A_110, Source: Github

This is obviously not the full configuration of the GPU, but a number of active GPU core clusters (Compute Units) on this specific SKU. In order to keep good yields, AMD needs to disable a part of the GPU to account for possible defects in production. The full Aldebaran GPU is rumored to feature 128 Compute Units.

Considering the settings of different Shader Engine and CU, Aldebaran / MI200 is an MCM configuration with 2 GPU dies, so if the setting is symmetric for each die instead of Shader Engine, each die will have 4 SEs. It is possible to have (56 CUs), and disable each one of them to make a total of 110 CUs.

— Coelacanth’s Dream

It is unclear if AMD is planning to double the FP32 core count on CDNA2 architecture, but assuming that they do, with a theoretical 1500 MHz GPU clock the accelerator would offer have a single-precision compute performance of 42.2 TFLOPS, 1.82x more than MI100. If that isn’t the case, then MI200 would have to have at least a 1650 MHz clock to reach the same FP32 throughput of 23 TFLOPs.

In the case of HPC accelerators such as MI200, the FP64 performance is far more important. According to previous leaks, MI200 is to feature full-rate FP64 performance, which means either doubling or quadrupling the performance over MI100, depending on the architecture.

The MI200 is confirmed to launch this year . This is AMD’s first multi-chip graphics processor with two active dies. It is expected to feature 128GB (4x as much as the MI100) of faster HBM2e memory.

Source: ROCm Github via Coelacanth’s Dream