JEDEC SPHBM4 cuts HBM4 interface from 2048 to 512 data signals

JEDEC has published JESD330-4, the completed specification for Standard Package High Bandwidth Memory 4, or SPHBM4. The memory standard is designed to deliver the same aggregate throughput as HBM4 while allowing memory stacks to connect through standard organic package substrates.

We first covered SPHBM4 in December 2025, when JEDEC confirmed that the specification was nearing completion. The final standard retains the same HBM4 DRAM dies and memory core layers but introduces a different interface base die.

512 data signals instead of 2048

A regular HBM4 interface uses 2048 data signals. SPHBM4 reduces this to 512 signals and compensates for the narrower connection with higher interface frequencies and 4:1 serialization.

JESD330-4 SPHBM is architected to operate at the same aggregate data throughput as HBM4 using fewer pins by operating at a higher frequency. Where the HBM4 interface has 2048 data signals, when published, SPHBM4 will define 512 data signals with 4:1 serialization to achieve the same bandwidth. This change allows the relaxed bump pitch required for connection to organic substrates.

— JEDEC

Each SPHBM4 data connection therefore transfers four times as much data over time. JEDEC says this allows the interface to maintain HBM4-class aggregate bandwidth while using the wider bump pitch required by organic substrates.

The memory capacity available from each stack remains the same because SPHBM4 uses standard HBM4 core layers. Organic substrate routing also supports longer connections between the processor and memory, which may allow accelerator designers to place more memory stacks around the SoC.

SPHBM4 does not replace HBM4 inside the memory stack. It changes how those dies communicate with the processor and how they can be integrated into the package. JEDEC has not announced products or deployment dates based on the completed JESD330-4 standard.

Source: JEDEC PR

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