AMD today announced the 6th Gen EPYC "Venice" server processors powered by the "Zen 6" CPU microarchitecture. The family includes a set of four distinct product lines, the EPYC 9006 (Socket SP7) for mainline servers with market leadership in core-counts and performance; the EPYC 9006 (Socket SP8) for enterprises with optimized performance per node; EPYC 9006X SP7 for high performance computing accelerated by larger CPU caches; and the EPYC 9006 LP "Verano" processors for AI host nodes powered by LPDDR memory.

The EPYC 9006 "Venice" family offers CPU core counts of up to 96-core/192-thread on chips with "Zen 6" cores, and up to 256-core/512-thread on chips with compacted "Zen 6c" cores. "Venice-X" HPC processors with 3D V-Cache offer up to 1,152 MB of L3 cache per socket. AMD has significantly upgraded the memory sub-system of these processors, giving Socket SP7 a 16-channel DDR5 memory interface with native support for DDR5-8000 RDIMMs, support for MRDIMMs with up to DDR5-12800 speeds. Specific variants also come with 24-channel LPDDR5X interfaces that support field-replaceable SOCAMM2 modules.