With TSMC's CoWoS advanced capacity egregiously constrained, and Intel's more nimble EMIB attracting a growing volume of orders, the Taiwan-based chipmaker has realized that it needs to change course to retain its competitive edge. And, it has chosen to do so by attempting to clone some elements of Intel's novel approach to advanced packaging, as per the reporting by The Information.

For the benefit of those who might not be aware, TSMC's Chip-on-Wafer-on-Substrate (CoWoS-S) packaging solution uses large, expensive silicon interposers to connect processors with High Bandwidth Memory (HBM). This is essentially a full-surface silicon interposer layer, replete with a uniform grid of micro-bumps across the entire bottom surface of the die, where they serve as an interconnect medium.

TSMC revamped this approach with CoWoS-L, which scraps the massive, continuous sheet of silicon interposer entirely, replacing it with a flexible, lower-cost Redistribution Layer (RDL) substrate. What's more, underneath this substrate, tiny localized silicon bridges - called Local Silicon Interconnects (LSI) - are embedded only at the precise boundaries where chiplets need to exchange dense data. This approach combines the high-speed data transmission of silicon with the massive, cost-effective surface area of organic RDL substrates .

Even so, Intel's Embedded Multi-die Interconnect Bridge (EMIB) is, in some respects, much more efficient than TSMC's CoWoS-L, connecting multiple silicon chips (chiplets) inside a single processor package using tiny silicon "bridges" embedded directly inside the organic substrate, with high-density micro-bumps placed only at the edges where the chiplets meet the bridge.

Basically, instead of routing signals through a massive, expensive silicon layer or a RDL that spans the entire chip, EMIB acts like a localized micro-highway placed only where two chips need to talk to each other.

To get an idea of the inherent efficiency of Intel's approach, consider the fact that the EMIB uses no middle-man layer. The chiplets sit directly on the organic substrate and link together over the buried bridges via a single attachment process.

In contrast, TSMC's CoWoS-L relies on a completely separate Redistribution Layer (RDL) interposer, with Local Silicon Interconnect (LSI) bridges embedded inside this intermediate carrier. This RDL-plus-bridge sandwich is manufactured on a traditional circular silicon wafer and then attached to an organic substrate below it. It requires two distinct assembly and attachment steps.

What's more, Intel's next-gen EMIB-T features Through-Silicon Vias (TSVs) drilled directly through the embedded silicon bridges. These vertical routing channels allow power and high-speed signals to flow straight up from the bottom of the chip package, through the bridge, and directly into the processors or memory sitting on top, enabling 3D stacking.

It's hardly a surprise, therefore that TSMC is now looking at Intel's EMIB as a source for inspiration. According to The Information, TSMC is now developing an "EMIB-like" packaging solution with Kinsus Interconnect Technology Corp. While details are scarce at the moment, we would hazard a guess that TSMC is looking to jettison the Redistribution Layer entirely, adopting EMIB-like silicon bridges instead.

With TSMC's CoWoS-L capacity sold out through 2026 and well into 2027, and lead times stretching to 78 weeks in some cases, the chip fabrication giant clearly needs an alternate approach to prevent Intel from gaining ground.

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