Intel appears laser-focused on operationalizing its new Ohio fab complex by 2031, and is willing to award generous bonuses to achieve that overarching goal. Meanwhile, the tailwinds also appear to be aligning on Intel's EMIB-T packaging, with only the substrate yields now left as the sole unsolved piece of the puzzle.

Disparate tailwinds are finally beginning to coalesce for Intel, indicating that its Ohio fab remains on schedule, and its EMIB-T advanced packaging is now poised to challenge TSMC's CoWoS-L

For the benefit of those who might not be aware, Intel is building a gigantic 1,000-acre fab complex in Ohio for its 'Angstrom era' process nodes, dubbed 18A and 14A.

To expedite work on this critical complex, Intel is now apparently paying generous overtime bonuses, aiming to operationalize high-volume 14A production by 2031 .

Meanwhile, we reported recently that TSMC was developing an EMIB-like advanced packaging solution to complement its bulkier CoWoS-L offering. For the benefit of those who might not be aware, Intel's EMIB connects multiple silicon chips (chiplets) inside a single processor package using tiny silicon "bridges" embedded directly inside the organic substrate, with high-density micro-bumps placed only at the edges where the chiplets meet the bridge.

The EMIB-T takes this approach a step further by sporting Through-Silicon Vias (TSVs) drilled directly through the embedded silicon bridges. These vertical routing channels allow power and high-speed signals to flow straight up from the bottom of the chip package, through the bridge, and directly into the processors or memory sitting on top, enabling 3D stacking. Do note that Intel's EMIB-T is around 50 percent cheaper than TSMC's CoWoS.

As such, Intel now expects to start offering its EMIB-T packaging solution in bulk in 2027, with package yields already approaching the 90 percent level. The only lingering obstruction, however, relates to substrate yield that is currently stuck at 50 percent.

As a refresher, the substrate used within Intel's EMIB-T consists of:

1. The base organic panel that features precision-drilled cavities where the silicon bridges are placed, and manufactured by Ibiden (primary anchor), Shinko, Unimicron, and AT&S.
2. Dielectric Build-up Layer, which are insulation layers laminated directly over the embedded bridges, and utilize industry-standard Ajinomoto Build-up Film (ABF).
3. The silicon bridges themselves that contain Through-Silicon Vias (TSVs) to route power vertically.

It is this substrate that is currently acting as a drag on Intel's plans for volumetric EMIB-T packaging services. Even so, Unimicron recently reiterated that the EMIB-T remains an early-stage platform, with rapid ramp-up and yield improvement currently the key priorities.

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