Samsung pitches zHBM with 8x HBM5 performance, but it is still only a concept
© Samsung Samsung used FMS 2026 to present a broad roadmap covering HBM4E, HBM5, LPDDR5X-PIM, 400-layer NAND and two new concepts called zHBM and zNAND-O . The presentation reads more like a pitch to customers and investors than a product announcement, since Samsung provided no launch dates for most of the technologies.
Samsung wants to stack HBM above AI chips
The main announcement is zHBM, which places stacked memory directly above an AI accelerator. Current HBM packages are normally installed beside the processor, so Samsung wants to shorten the connection between the memory and compute chip.
Samsung claims a future zHBM interface could deliver around eight times the performance of HBM5. The company also expects more than ten times the memory density, three times the energy efficiency and over 50% lower thermal resistance. These claims are based on a concept model, with no confirmed product, customer or production schedule.
© Samsung 
© Samsung The timing follows the recent High Bandwidth Flash announcement from Sandisk and SK hynix. HBF uses stacked NAND to add more memory capacity close to AI processors, while zHBM focuses on placing DRAM directly above them. HBF already has an open technical specification, while Samsung’s zHBM remains a longer-term proposal.
Samsung also shows 400-layer NAND
Samsung also introduced V10 BV-NAND with more than 400 layers. Its Bonding V-NAND architecture builds the memory cells and peripheral circuits on separate wafers before joining them together. Samsung claims this increases density by around 58% compared with V9 NAND, but detailed performance figures and availability were not disclosed.
If only Samsung could announce breakthrough technology that reduces the cost of GDDR6/GDDR7 production, that would be even better.
| HBM vs. HBF vs. Samsung zHBM | |||
|---|---|---|---|
| HBM | HBF | zHBM | |
| Memory type | DRAM | NAND flash | DRAM |
| Placement | Beside the accelerator | Close to the accelerator | Above the accelerator |
| Architecture | 2.5D packaging | Stacked high-bandwidth flash | 3D vertical stacking |
| Main focus | High bandwidth and low latency | Higher capacity at lower cost | Higher density and shorter connections |
| Status | Shipping technology | Open specification | Samsung concept model |
Source: Samsung
