Just a few weeks after AMD inked a deal with Cerebras to boost the inference capabilities of the upcoming Helios rack-scale system, it has acquired Taalas, a startup that designs chips specifically for inference-related workloads.

AMD has just signed an agreement to acquire Taalas in a move designed to complement its Helios systems. For the benefit of those who might not be aware, Taalas eliminates the so-called memory wall - an increasingly common situation where the GPUs sit idle as they wait for the appropriate data to arrive to then start crunching numbers - by hardwiring a given AI model into individual transistors, courtesy of a proprietary digital architecture that is capable of storing 4 bits of data and executing math operations using a single transistor.

Basically, the Taalas HC1 chip features shared hardware blocks that permanently and constantly pre-compute all 16 possible products for a quantized 4-bit model weight. Because every possible math outcome is already happening live across the chip, the individual transistor doesn't actually do any math but acts as a physical router.

To delve deeper, each specific weight of the AI model here is represented by a single 'Mask ROM' transistor - during the manufacturing process, a microscopic physical wire (a metal layer mask) is etched to physically connect that transistor to one of the 16 pre-computed product lines. When data flows through the chip, the transistor simply selects the correct pre-calculated mathematical channel and passes it to the adder. Therefore, Taalas' HC1 chip is capable of generating an astonishing 16,000 to 17,000 tokens per second per user by using this setup.

This approach is somewhat similar to the Groq LPU , which uses small isolated pools of the SRAM, and where AI model weights are hard-baked directly into the SRAM, completely bypassing the concept of a memory cache.

AMD's decision to acquire Taalas complements its integration of the Helios system with Cerebras' Wafer-Scale Engine, which places an entire AI supercomputer’s worth of memory and compute onto a single, giant, interconnected sheet of silicon, and where hundreds of thousands of compute cores and tens of GBs of SRAM connect seamlessly, allowing data to move efficiently without ever hitting external network bottlenecks.

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