Hindered by the ongoing capacity constraints at TSMC, AMD will strike up a foundry deal with its arch-nemesis Intel, as per the latest commentary from analysts over at UBS.
Separately, Goldman Sachs seems to have turned sour on the prospects of AMD ever catching up to NVIDIA on data center racks, with the latter likely to ship 10x, 7x, and 9.8x as many racks in 2026, 2027, and 2028, respectively.
AMD appears destined for a perennial underdog status on data center racks, and might have to tap its arch-nemesis Intel to maintain momentum on shipments
According to UBS, Google, Apple, AMD, and SpaceX will all tap Intel's EMIB-T packaging technology by striking individual foundry deals, which should give Intel a massive tailwind.
Intel now expects to start offering its EMIB-T packaging solution in bulk in 2027, with package yields already approaching the 90 percent level . The only lingering obstruction, however, relates to substrate yield, which is currently stuck at 50 percent.
Do note that EMIB-T is around 50 percent cheaper than TSMC's CoWoS, and sports Through-Silicon Vias (TSVs) drilled directly through the embedded silicon bridges. These vertical routing channels allow power and high-speed signals to flow straight up from the bottom of the chip package, through the bridge, and directly into the processors or memory sitting on top, enabling 3D stacking.
Separately, Goldman Sachs has just published a sobering take on AMD's data center rack momentum, which is expected to remain substantially subdued relative to NVIDIA's. As such, NVIDIA will ship 50,000 racks in 2026 vs. AMD's shipment volume of 5,000 units, 92,000 racks in 2027 vs. AMD's 13,000, and 148,000 racks vs. AMD's 15,000.
Do note that, to boost the attractiveness of its rack-scale offerings, AMD has recently partnered with Cerebras , where Cerebras' Wafer-Scale Engine places an entire AI supercomputer’s worth of memory and compute onto a single, giant, interconnected sheet of silicon, and where hundreds of thousands of compute cores and tens of GBs of SRAM connect seamlessly, allowing data to move efficiently without ever hitting external network bottlenecks.
AMD has also inked an agreement to acquire Taalas , which physically wires a given AI model's math values into the paths of the transistors. Consequently, the Taalas chip doesn't have to "load" anything or fetch data from memory because the circuit is the memory and the brain combined. But the chip only works for the model it is designed for.
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