Cerebras, the creators of the wafer-scale engine chip, have released their latest CS-4 solution that packs its brand-new WSE-3 Turbo chip.
Back in 2024, Cerebras unveiled its 3rd Gen Wafer Scale Engine , or WSE-3. This wafer acts as a single chip and offers lots of compute capabilities. Cerebras has been doing Wafer-Scale chips since their advent, and today, the company unveiled the next chapter in its wafer-scale journey.
“In AI, speed is productivity,” said Andrew Feldman, CEO and co-founder of Cerebras. “Historically, fast inference meant using smaller and less capable models. Cerebras CS-4 delivers industry-leading speeds on the largest frontier models, fundamentally changing the paradigm. Every aspect of the design has been optimized to deliver the highest speeds with massive throughput. With the CS-4, AI is so fast that it fundamentally reshapes product experiences.”
Starting with this new chip, the WSE-3 Turbo, or WSE-3T, is a follow-up to the WSE-3. It retains the "largest AI processor" positioning and also packs the same number of transistors and cores, at 4 trillion and 900,000, respectively. The entire chip measures 46,225mm2 and also comes with 44 GB of SRAM, which is directly integrated on the same wafer.
In terms of some high-level performance aspects, the WSE-3T is said to offer double the compute in AI with 125 PFLOPs (250 PFLOPS with sparsity) per wafer, and bandwidth increases to 43.2 PB/s. The on-chip fabric offers 53.5 PB/s of bandwidth while the off-chip I/O offers 2.4 Tb/s bandwidth. Updates to the wafer-scale engine also help slash latency from 5ms to 2ms.
That's all for the chip that is being disclosed for now, but today's AI is different. Chips are a vital component, but AI customers don't go after chips; they go after systems and a one-stop solution. As such, Cerebras is outfitting its latest CS-4 rack-scale solution with the WSE-3T chips.
According to Cerebras, CS-4 is built on its new Nexus Platform Architecture, which centers around a modular concept that includes three layers: Compute, Power, and I/O. Each rack features a pluggable backpack design so that the compute subsystem goes into the rear as a "backpack" that is attached vertically to the power array.
Each of these self-contained wafer-scale "backpacks" folds the power conversion, direct liquid cooling, high-speed I/O, and control systems into a compact package.
The new design also helps eliminate power losses almost entirely by moving power conversion closer to the wafers. Since losses are reduced, more power can be directed to the WSE chips, & that results in 2x power for the engine to feed on, enabling higher frequencies & faster compute.
The company is also claiming some big compute throughput capabilities in models such as GPT-OSS 120B. A single CS-4 rack offers over 4,400 tokens per second in this model. A GPU-based AI solution was also compared. What took CS-4 one second to generate, the GPU rack took 30 secs.
Overall, Cerebras is claiming a hefty 10x increase in throughput per watt for CS-4 versus CS-3. Each CS-4 rack will offer three WSE-3T (Turbo) chips, pumping out 750 PFLOPs of AI compute, 7.2 Tb/s of I/O bandwidth, and 129.6 PB/s of SRAM bandwidth. With the new interconnect solution, AI factories can scale CS-4 to large-scale clusters to support models with over 50 trillion parameters.
The first CS-4 shipments with WSE-3T are expected to begin this quarter, and NVIDIA is one of the main rivals these are meant to tackle. Cerebras has also partnered with AMD to utilize its wafer-scale rack solutions alongside the Helios AI rack to drive higher AI throughput, similar to how NVIDIA utilizes Groq 3 LPX racks to offload the KV cache to the large SRAM housed on these chips.
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