With the next two generations of Intel's processors - Nova Lake and Razor Lake - maintaining or even enhancing their fabrication footprint at TSMC, at least as per recent leaks, AMD's ability to secure marginal capacity within TSMC's increasingly constrained fabs now stands at a disadvantage.
We already know that Intel is preparing to start mass producing its Nova Lake chips around January 2027. While these new family of chips were initially believed to rely entirely on Intel's own 18A process, recent tidbits have suggested that Intel might split the production load between its own 18A process and TSMC's N2P, as reiterated just today by the Commercial Times , which has added two additional tidbits:
- The laptop versions of Nova Lake chips might not materialize until the Razor Lake-HX generation.
- The Nova Lake chips will introduce bLLC (Big Last-Level Cache), which is meant to compete directly with AMD's X3D chips. As per related reports, the top-tier 52-core family models will feature up to 288 MB of cache, while the 28-core variants will feature 144 MB of cache.
What's more, Intel's Razor Lake chips will also split the production load between its in-house process and TSMC's N2X process, which is a high-performance extension of the Taiwan-based fabrication giant's N2 platform, targeting high-frequency CPUs, AI, and HPC, with technology shifting from FinFET to nanosheet.
This situation has, of course, complicated AMD's efforts to secure additional capacity at TSMC, which is already severely constrained. At the other end of the spectrum, Intel's ongoing reliance on TSMC suggests its 18A process is still not entirely ready to shoulder the full burden of its ambitions.
Meanwhile, we reported earlier today that Intel's Core Ultra 9 4950K chip , which is a part of its Nova Lake-S CPU family, and likely features 28 cores - a mix of 8 P-Cores and 20 E-Cores (16 E + 4 LPE) - and offers single-core performance of ~1,000 points and multi-core performance of ~20,000 points on CPU-Z.
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