Rapidus has laid out its advanced packaging roadmap at the 2026 OCP APAC Summit, with eight-reticle-size interposers and 600 x 600 mm panel-level processing as the targets for around 2030. The roadmap was presented by Rapidus Design Solutions CTO Rozalia Beica and shows steps through interposer sizes from four reticles (3,320 mm²) to six (4,980 mm²) and eventually eight (6,640 mm²) by 2030. The 600 x 600 mm panel format is the most important target of that plan as the yield advantage at panel scale is substantial. CTO Beica illustrated the output difference in a simple manner: an eight-reticle interposer yields four units on a standard 300 mm wafer, nine on a 300 x 300 mm panel, 36 on a 510 x 515 mm panel, and 49 on a 600 x 600 mm panel. Taiwanese rival TSMC has its own CoWoS interposer roadmap showing plans aiming for 5.5 reticles in 2026, 9.5 in 2027, and 14 reticles in 2028. However, the two companies are taking different manufacturing approaches. Rapidus is betting on panel-level processing rather than wafer-based scaling.

The 600 mm panel strategy is underway, with Rapidus demonstrating the format and working with Lam Research's Kallisto electroplating system to develop 2.xD packaging with redistribution layers formed on 600 mm glass carriers. We reported in late 2025 that Rapidus produced the first large-format glass interposer prototype and plans to enter mass production in 2028. Last year, Rapidus taped out a 2 nm GAA test chip using ASML EUV tools claiming a transistor density of 237 MTr/mm². Its FY2026 plan brings the Rapidus Chiplet Solutions pilot line into full operation to verify 2.xD and 3D packaging processes.