AMD EPYC Genoa with 12-channel DDR5-5200 memory support
A few days after AMD added Linux patches confirming AMD EPYC Genoa memory configuration, two sources have corroborated the story by sharing yet undisclosed documents.
The patches confirmed that the AMD EPYC “Genoa” which is based on Zen4 microarchitecture will indeed support 12-channel 1DPC DDR5 memory. However, this is not exactly news at this point, but the first time AMD themselves confirmed it. The reason why this was known for a few months now is that some documents that have been part of the Gigabyte/AMD leak have actually included extensive information on the next-gen EPYC series. Until now, those documents have not been published.
The first document which was posted by Hans de Vries shows a diagram of Titanite 2P2G system with dual Genoa SP5 CPU, each supporting up to twelve DDR5 modules at the same time. We do not know how accurate and up-to-date this diagram is, however one should note that according to this picture, Genoa was expected to support Gen-Z, but in the end, AMD decided to support the CXL standard instead (as pictured above). The Gen-Z Consortium has confirmed it will transfer the specifications of the interface to the CXL consortium, which renders Gen-Z pretty much abandoned at this point. Regardless of whether that’s GenZ or CXL, it will still rely on the PCIe Gen5 standard.
Titanite 2P2G system with dual Genoa SP5 CPU, Source: Hans de Vries
ComputerBase posted a screenshot from the AMD Genoa memory support presentation. It confirms that the next-gen EPYC CPU is to support up to 5200 MT/s through 16-layer memory modules which capacities up to 1.5 TB (LRDIMM type). Interestingly though, the platform is capable of supporting up to 12TB with 3DS RDIMM modules (3DS uses through-silicon vias), however, the speed will be limited to 4000 MT/s.
AMD EPYC Genoa Memory Support, Source: ComputerBase
AMD confirmed that Genoa is now sampling to customers and it is on track to launch in 2022. It will be accompanied by Bergamo based on Zen4c microarchitecture which will be compatible with the SP5 socket and platform.
| AMD EPYC Processor Series | ||||||
|---|---|---|---|---|---|---|
| 7001 “Naples” | 7002 “Rome” | 7003 “Milan” 7003 “Milan-X” | 7004 “Genoa” | 7004 “Bergamo” | 7005 “Turin” | |
| Launch | 2017 | 2019 | 2021 | 2022 | 2022 | 2023/2024 |
| Architecture | 14nm Zen | 7nm Zen2 | 7nm Zen3 | 5nm Zen4 | 5nm Zen4c | Zen5 |
| Socket | SP3 (LGA4094) | SP3 (LGA4094) | SP3 (LGA4094) | SP5 (LGA-6096) | SP5 (LGA-6096) | SP5 (LGA-6096) |
| Modules/Chiplets | 4x CCD | 8x CCD + 1x I/0 | 8x CCD + 1x I/O | 12x CCD + 1x I/O | 12x CCD + 1x I/O | TBC |
| Max Cores | 32C/64T | 64C/128T | 64C/128T | 96C/192T | 128C/256T | 256C/512T |
| Max Clock | 3.8 GHz | 3.9 GHz | 4.1 GHz | TBC | TBC | TBC |
| Memory Support | 8ch DDR4-2666 | 8ch DDR4-3200 | 8ch DDR4-3200 | 12ch DDR5-5200 | 12ch DDR5-5200 | 12ch DDR5-6000 |
| PCIe Lanes | 128x Gen3 | 128x Gen4 | 128x Gen4 | 128x Gen5 | TBC | TBC |
| Max cTDP | 200W | 280W | 280W | 400W | TBC | 600W |
Source: ComputerBase , @HansDeVriesNL via TechPowerUP