European Space Agency has formed a group with researchers at ETH Zürich and the University of Bologna to design and develop a RISC-V processor aimed at boosting computational capabilities in space. The task was assigned to the Parallel Ultra Low Power (PULP) Platform project, which created open-source RISC-V silicon with actual tape-outs. Called Occamy, it is a high-performance AI chip designed for efficiency. Built on GlobalFoundry's 12 nm GF12LPP low-power process, the chiplet design is placed on top of a passive 65 nm interposer. Based on RISC-V ISA, Occamy uses as many as 231 cores with 32-bit word length on each of two chiplets, totaling 432 32-bit cores. Combined with 64-bit Floating Point Units (FPUS), the Occamy chip can achieve 0.768 TeraFLOPS at FP64, 1.536 TeraFLOPS at FP32, 3.072 TeraFLOPS at FP16, and 6.144 TeraFLOPS at FP8 precision.

Featuring about one billion transistors, they are packed in a 72 square millimeter solution, which is placed on a 52.5x45 mm carrier PCB for Fan-Out mounting. Being a chiplet design, Occamy uses 2.5D integration and features two 16 GB HBM2E DRAMs from Micron. Additionally, the chip dedicates a compact 32-bit RISC-V control chip to route the information of the rest of the AI-enabled cores. The single Occamy die uses 10 Watts at 1000 MHz speed, so two dies plus HBM memory would double the power usage in the final chip. Not only tested on AMD Xilinx Virtex UltraScale+ HBM FPGAs and the Virtex UltraScale+ VCU1525 FPGA but the chip has also been taped out in less than 15 months. Taped out on the 1st of July 2022, the chiplet started the development journey on the 20th of April 2021. The entire chip is being assembled, and more information will be available in Q3 of 2023.