AMD announced a range of new products today at its Data Center and AI Technology Premiere event here in San Francisco, California. The company finally shared more details about its 5nm EPYC Bergamo processors for cloud native applications, and the chips are shipping to customers now.
AMD also announced its Instinct MI300 processors that feature 3D-stacked CPU and GPU cores on the same package with HBM, a new GPU-only MI300X model that brings eight accelerators onto one platform that wields an incredible 1.5TB of HBM3 memory, and its EPYC Genoa-X processors with up to 11GB of L3 cache. All three of these products are available now, but AMD also has its EPYC Sienna processors for telco and the edge coming in the second half of 2023.
AMD EPYC Bergamo
AMD's 128-core EPYC Bergamo processors are the industry's first x86 could native CPUs, which are designed for the utmost core density with an optimized Zen 4c core that halves the area needed for each core. These chips will compete with Intel's 144-core Sierra Forrest chips, which mark the debut of Intel's Efficiency cores (E-cores) in its Xeon data center lineup, and Ampre's 192-core AmpereOne processors, not to mention the custom silicon being developed or employed by Google and Microsoft.
All of these offerings are designed to maximize power efficiency for highly-parallel latency-tolerant workloads, like high-density VM deployments, data analytics, and front-end web services, by offering higher core counts than standard data center chips and a lower frequency and power envelope.
AMD's Bergamo has 128 cores and drops into server platforms that utilize the same socket SP5 as the standard 96-core EPYC Genoa processors. Like their standard counterparts, Bergamo supports 12-channel memory running at DDR5-4800. AMD forges the chips by combining chiplets with Zen 4c cores with the company's existing 'Floyd' central I/O die, thus tying the compute units to memory and I/O to a chiplet based on an older process node.
| Row 0 - Cell 0 | EPYC 9654 | EPYC 9754 | EPYC 9734 |
| Design | Genoa | Bergamo | Bergamo |
| Microarchitecture | Zen 4/Persephone | Zen 4c/Dionysus | Zen 4c/Dionysus |
| Cores/Threads | 96/192 | 128/256 | 112/224 |
| L1i Cache | 32KB | 32KB | 32KB |
| L1d Cache | 32KB | 32KB | 32KB |
| L2 Cache | 1MB | 1MB | 1MB |
| Total L2 Cache | 96MB | 128MB | 112MB |
| L3 Cache per CCX | 32MB | 16MB | 16MB |
| Total L3 Cache | 384MB | 256MB | 256MB |
| CCD | Durango | Vindhya | Vindhya |
| CCD Count | 12 | 8 | 8 |
| CCX per CCD | 1 | 2 | 2 |
| Cores per CCD | 8 | 16 | 14 |
| I/O Die | Floyd | Floyd | Floyd |
| Memory Channels | 12 | 12 | 12 |
| Rated Memory Speed | DDR5-4800 | DDR5-4800 | DDR5-4800 |
| Memory Bandwidth | 460.8 GB/s | 460.8 GB/s | 460.8 GB/s |
| PCIe 5.0 Lanes | 128 | 128 | 128 |
| TDP/Max TDP | 360W/400W | 360W/400W | 360W/400W |
| Socket | SP5 | SP5 | SP5 |
| Scalability | 2P | 2P | 2P |
*not all specs in the above table are confirmed.
AMD claims a 2.7X increase in energy efficiency with the Bergamo chips.
AMD shared a few broadstrokes about the Bergamo architecture, including that it has a core + L3 cache are of 2.48mm^2, which is 35% smaller than the 2.48mm^2 that it achieved on the same process node with the standard Zen 4 cores. AMD employs eight 16-core CCDs to reach the peak core count of 128 cores.
We're learning more deep-dive architectural details of the chips today, stay tuned for further coverage.