A leaked presentation slide by AMD for its Ryzen 5000 series "Zen 3" processors reveals details of the processor's memory interface. Much like the Ryzen 3000 series "Matisse," the Ryzen 5000 series "Vermeer" is a multi-chip module of up to 16 CPU cores spread across two 8-core CPU dies, and a unified I/O die that handles the processor's memory-, PCIe, and SoC interfaces. There are three configurable clock domains that ensure the CPU cores are fed with data at the right speed, and to ensure that the MCM design doesn't pose bottlenecks to the memory performance.

The first domain is fclk or Infinity Fabric clock. Each of the two CCDs (8-core CPU dies) has just one CCX (CPU core complex) with 8 cores, and hence the CCD's internal Infinity Fabric cedes relevance to the IFOP (Infinity Fabric over Package) interconnect that binds the two CCDs and the cIOD (client I/O controller die) together. The next frequency is uclk, or the internal frequency of the dual-channel DDR4 memory controller contained in the cIOD. And lastly, the mclk, or memory clock is the industry-standard DRAM frequency.