Last week at the IEEE International Electron Devices Meeting, the world's top-three semiconductor foundries, TSMC, Intel (Intel Foundry Services or IFS), and Samsung Electronics, demonstrated their respective approaches to an evolutionary new transistor device called the CFET, or complementary field-effect transistors. A CFET is a kind of 3-D transistor that stacks both kinds of FETs needed for CMOS logic. All three fabs are transitioning from FinFET to nanosheets, or GAAFETs (gates all-around FETs).

While FinFETs use vertical silicon fins, with gates controlling the flow of current through them; while in a nanosheet, the vertical fin is cut into a set of ribbons, each surrounded by the gate. A CFET is essentially a taller nanosheet device in which uses half of the available ribbons for one device, and the other half for another. This device builds the two types of transistor, nFETs and pFETs on top of each other, in an integrated process. CFETs are the evolutionary next step to conventional GAAFETs, and it's predicted to enter mass production only 7-10 years from now. By that time, the industry will begin to feel the pushback from technological barriers preventing development beyond 10 angstrom-class nodes.