This soft-core implementation of a RISC-V processor from AMD is compatible with the AMD-Xilinx Vivado and Vitis tooling and can be leveraged on AMD's FPGA hardware and adaptive SoCs. For those that missed the original announcement on this AMD 32-bit RISC-V soft-core processor can find out more information on Xilinx.com .
With the upcoming Linux 6.8 kernel, the mainline tree will add the DeviceTree bindings for the MicroBlaze V. The patch has been queued into the RISC-V "for-next" branch ahead of the Linux 6.8 merge window opening in a few days.
It's just the DeviceTree bits needed and interestingly is reusing the MicroBlaze support. MicroBlaze as a reminder is the Xilinx soft-core processor for their FPGAs that's been around for two decades and is RISC-based. On the Linux kernel mailing list it was raised about being "hardware compatible" with the original MicroBlaze and the reuse of MicroBlaze kernel code for this new RISC-V-based soft-core design given the different ISA. This re-use of existing Linux MicroBlaze code was explained as:
"It is still the same MicroBlaze pipeline just with a different instruction decoder up front. The “macro ops” are now RISC V instructions, the “micro-ops” are still the same operations in the various MicroBlaze pipeline stages."
So for Linux 6.8 it's just the new DT bits needed for this AMD 32-bit RISC-V soft-core that is otherwise compatible with the "classic" MicroBlaze.