AMD Ryzen 9000X3D Series to feature three models

AMD is reportedly not planning to change the 3D V-Cache sizes on its next-gen Ryzen 9000 series.

Later this month, AMD will launch its first Zen5-based desktop CPUs for the existing AM5 socket. The fifth generation of Zen will maintain the same core count as its predecessor, the Ryzen 7000 series. According to a report from Wccftech , it will also retain the same 3D V-Cache size for the upcoming releases.

The initial lineup of the 9000X series will not include 3D V-Cache parts, but these SKUs are reportedly set to launch as early as September . AMD has already mentioned some details about the new X3D series, suggesting there will be notable differentiators within this lineup. Don Waligroski’s statement hinted at possible changes to the 3D V-Cache size, which currently stands at 64MB.

Contrary to earlier reports, Wccftech now states that AMD will not change the cache capacity. Instead, AMD is supposedly planning a lineup similar to the 7000X3D series, which will consist of three SKUs.

AMD Ryzen 9000X3D Caches

• Ryzen 9 9950X3D – 32 MB Per CCD (64 MB L3) + 64 MB 3D V-Cache (128 MB) + 16 MB L2 + 1 MB L1
• Ryzen 9 9900X3D – 32 MB Per CCD (64 MB L3) + 64 MB 3D V-Cache (128 MB) + 12 MB L2 + 768 KB L1
• Ryzen 7 9800X3D – 32 MB per CCD (32 MB L3) + 64 MB 3D V-Cache (96 MB) + 8 MB L2 + 512 KB L1

The total combined cache at L2 and L3 levels will again top out at 144MB. Since AMD did not alter the size of the L2 cache, these will be identical in comparison to the 7000X3D models.

Coming to the amount of 3D V-Cache, the AMD Ryzen 9 9950X3D will feature a total of 128 MB of L3 cache with a single 3D V-Cache boosted Zen 5 CCD which would feature a 64 MB stack and 64 MB from the core itself. The AMD Ryzen 9 9900X 12-Core will also feature a similar configuration but it will come with a lower overall cache amount due to its L2 being 12 MB and L1 being 768 KB versus the 16 MB L2 and 1 MB L1 on the 9950X.

— Wccftech

It’s a bit surprising that AMD still intends to launch a 12-core model, which has been among the least popular X3D models. Since AMD isn’t employing dual 3D V-Cache for each compute chiplet, at least half of the cores again won’t benefit from the faster cache. Similarly, AMD was expected to introduce dual 3D V-Cache for each chiplet in the 16-core variant, which would eliminate the need for complex core affinity algorithms for different tasks.

So far, the only change aside from the microarchitecture for the new X3D models would be access to overclocking . The full scope of this enablement is unclear; some expect it to be very limited to protect the sensitive 3D V-Cache.

Source: Wccftech