The patches posted today by Intel's Haochen Jiang for the GCC compiler are SM4 EVEX instructions, AMX-AVX512, AMX-TF32, AMX-TRANSPOSE, AMX-FP8, MOVRS, and AMX-MOVRS. All of these are now confirmed features with Diamond Rapids processors and also reflected within new ISA programming reference guides.
Diamond Rapids is bringing a number of additions particularly around AMX that has already proven quite beneficial for various AI workloads since its introduction back in Sapphire Rapids. With Diamond Rapids, AMX is seeing a number of new capabilities added, including for FP8 tiles and for converting FP32 elements to BF16, among other additions. The new MOVRS instructions are for move read-shared value.
This set of 7 patches posted this morning plumb in the new ISA features for the additional AMX instructions, SM4 EVEX extension, and MOVRS/PREFETCHRST2. The new ISA features for Diamond Rapids are documented in this updated PRM .
Intel's plan is for getting these patches plus a "-march=diamondrapids" target added in time for the GCC 15 compiler debuting as stable in early 2025. Kudos to Intel for their continued timely upstreaming of new CPU ISA features and new CPU family targets well in advance of product launches so that there can be stable, upstream compiler support for new CPUs ahead of the processors actually shipping to customers. Intel does a great job here with their timely upstreaming open-source work. Over in kernel space the Intel software engineers have also been busy adding in a variety of other new features and IDs needed for Xeon Diamond Rapids.
Intel Diamond Rapids as the successor to Xeon 6 Granite Rapids is expected to be out around late 2025.