The "request for comments" patches from Bytedance engineer Xu Lu allow for overcoming the limitation of the MMU and allow for a larger bage size on RISC-V beyond the current 4K page size.
"This patch series attempts to break through the limitation of MMU and supports larger base page on RISC-V, which only supports 4K page size now. The key idea is to always manage and allocate memory at a granularity of 64K and use SVNAPOT to accelerate address translation."
No performance benchmarks were shown of this new 64K page size option for RISC-V, but on ARM it can equate to a significant performance improvement for a 64K vs. 4K page size.
Those interested can find the 64K RISC-V page size kernel patch series with all 21 patches in full via the kernel mailing list .