Back in early 2023 an Xtensa back-end was added to LLVM for the Cadence Tensilica Xtensa IP. Xtensa is used for DSPs, micro-controllers, and this 32-bit RISC architecture is also used for other hardware like data processing engines. Two years after the LLVM back-end was introduced, the Clang C/C++ compiler has added Xtensa target support.

While Xtensa isn't too popular, there remains a devoted group of developers working on the LLVM/Clang support for this architecture. There also is the forked/downstream version of LLVM/Clang for Xtensa support. Merged this past week is now having upstream support in the Clang compiler for targeting Xtensa.

See this merge request for the discussions over the new target and the arguments still being made in favor of having the Xtensa support in mainline. This newly-merged code will be part of the LLVM 20.0 release in the early months of the new year.