Going on for a few years now has been some Mesa optimizations for AMD Ryzen CPUs and in particular L3 cache optimizations . There is now a fix to re-enable this support after it was mistakenly broken earlier this year.

Back in March and back-ported to stable with Mesa 21.0.2 was an effort to improve the AMD L3 cache calculation code . This was due to the prior code breaking on dual socket AMD EPYC systems checked, but it turns out that fix was broken itself.

AMD developer Marek Olšák landed a fix today in Mesa 21.2-devel and will be back-ported to Mesa 21.0/21.1 to re-enable the L3 cache pinning behavior.

Marek noted in the commit that fixes the L3 code from March, " fix (re-enable) L3 cache pinning. cores_per_L3 was uninitialized, so it was always disabled. Remove the variable and do it differently. " Whoops, at least it's fixed now.