JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced the publication of JESD209-6, the latest Low Power Double Data Rate 6 (LPDDR6) standard. JESD209-6 is designed to significantly boost memory speed and efficiency for a variety of uses including mobile devices and AI. The new JESD209-6 LPDDR6 standard represents a significant advancement in memory technology, offering enhanced performance, power efficiency, and security.

High Performance
To enable AI applications and other high-performance workloads, LPDDR6 employs a dual sub-channel architecture that allows for flexible operation while maintaining a small access granularity of 32 bytes. In addition, LPDDR6 key features offer:

• 2 sub-channels per die, 12 data signal lines (DQs) per sub-channel to optimize channel performance capabilities
• Each sub-channel includes 4 command/address (CA) signals, optimized to reduce ball count and improve data access speed
• Static efficiency mode designed to support high-capacity memory configurations and maximize bank resource utilization
• Flexible data access, on-the-fly burst length control to support 32B & 64B access
• Dynamic write NT-ODT (non-target on-die termination) enables the memory to adjust ODT based on workload demands, improving signal integrity