Universal Chiplet Interconnect Express (UCIe) Consortium, the open standard for interconnects between chiplets within a package, today announced the release of the UCIe 3.0 specification, marking the next stage in the evolution of its open chiplet standard. The new specification delivers significant performance enhancements, most notably support for 48 GT/s and 64 GT/s data rates, alongside incremental architectural updates to meet growing industry demand for high-speed, interoperable chiplet solutions.

The UCIe 3.0 specification also introduces enhancements such as runtime recalibration for improved power efficiency and extended sideband reach that supports more flexible multi-chip configurations. Additional manageability features like early firmware download and priority sideband packets increase system responsiveness and reliability. The specification's optional manageability features give companies the flexibility to implement only what they need, enabling broad adoption while allowing design customization without unnecessary silicon.