Intel has just unveiled new information on its next-gen Clearwater Forest "E-Core" Xeon CPUs with up to 288 cores, based on the 18A process node.

Intel's next-gen E-Core only "Xeon" family, codenamed Clearwater Forest, is making its way to servers soon. Just like how the Xeon 6 lineup was segmented into P-Core and E-Core flavors, such as Granite Rapids & Sierra Forest, we will see the next-gen Xeon family in P-Core only "Diamond Rapids" & E-Core only "Clear Water Forest" lineups. The P-Core family is optimized for performance & tackles more compute-intensive and AI workloads, while the E-Core only family is optimized for efficiency & tackles high-density / scale-out workloads.

In its Hot Chips 2025 presentation, Intel outlined that Clearwater Forest Xeon CPUs will be fabricated on the company's latest and greatest 18A process node, which is also being used by Panther Lake on the client side, arriving later this year. Some of the main highlights of the new Xeon E-Core CPU include:

• Intel's latest process node, 18A: Improved performance and power efficiency
• Intel's latest Efficiency Core Architecture: IPC uplift tuned for 18A process
• Intel Foveros Direct 3D Construction: Shorterpower-efficient routes, larger LLC
• Increased Memory Bandwidth: 12-Channel DDR5-8000

Starting with the process technology, Intel's Clearwater Forest is based on the aforementioned 18A node and utilizes Backside metal combined with gate-all-around to provide numerous benefits beyond just FET Z scaling. 18A brings lowered gate capacitance, which improves core logic power efficiency, higher cell density with over 90% cell utilization rates, improved signal routing, which helps reduce RC delay and further improves efficiency, and lastly, offers low-loss power delivery with losses being reduced by 4-5%.

Coming to the architecture, Intel is leveraging its Darkmont E-Core design for Clearwater Forest, which is an update to Sierra Glen E-Cores used by Sierra Forest. These cores offer:

• Smarter Front-End
• Deeper out of Order Engine
• Bigger Scalar & Vector Execution
• Enhanced Memory Subsystem

The front end features a 64kB Instruction cache, three 3-Wide instruction decoders that offer 50% more instruction bandwidth with nine decodes per cycle, and a much more accurate branch predictor, possibly using deep branch history and larger structure sizes.

The OOE (Out-of-Order Engine) sees an upgrade too, with 8-wide allocation (60% increase), with 16-wide retire (2x increase) for execution parallelism. The entry out-of-order window size is increased by 60% with 416 units, while 26 execution ports offer a 50% increase versus the prior generation.

The Execution Engine sees 26 execution ports to address a range of workloads, while dedicated hardware offers improved efficiency. The Integer and Vector Execution units are increased by 2x while Load Address Generation sees a 1.5x increase, and 2x uplift for Store Address Generation.

The core memory subsystem gets a 50% increase to Three-Load while the Two Store remains the same. The issuing of loads earlier could help reduce latency. Deep Buffering supports up to 128 outstanding L2 misses (2x increase). There are also advanced prefetchers on Clearwater Forest, while the list of Xeon E-Core specific features includes:

• L1 Data Cache ECC
• Data Poisoning Support
• Recoverable Machine Check
• Local Machine Check
• 52 physical address bits
• Core Lockstep

Intel is also leveraging a new modular architecture with Clearwater Forest "E-Core" Xeon CPUs. This includes 4 MB of Unified L2 cache with 17 latency cycles per four-core cluster for up to 288 MB of L2. The L2 cache also offers much higher bandwidth with up to 2x increase or 400 GB/s. In addition to these, the base tile also includes a bigger LLC, rated at up to 576 MB.

The IPC increase is rated at 17% as per measurements conducted in SpecIntRate'17. Each core shares 200 GB/s of bandwidth with the L2 cache, while a 35 GB/s fabric interconnect connects the clusters together.

Intel went all 3D when building Clearwater Forest, with a total of 12 CPU chiplets, which are fabricated on the 18A process node. These sit on three individual base tiles, which include the Fabric, LLC, memory controllers, and IO, & are based on Intel 3 process node. The interposer houses two I/O chiplets based on Intel 7 and features high-speed IO, fabric, and accelerators. The communication is handled by Intel's EMIB interconnect solution.

So in total:

• 12 E-Core CPU Chiplets (Intel 18A)
• 3 Base Tile Packages (Intel 3)
• 2 IO Chiplets (Intel 7)

Clearwater Forest also uses a monolithic mesh coherent fabric, which uses shorter routes, more metal resources, and a high-density interconnect for improved power efficiency.

In the end, Intel shares some performance aspects of a 2S Clearwater E-Core Xeon solution. The CPUs support 12-channel DDR5-8000 memory with up to 3 TB capacities in a dual-socket server, and up to 1300 GB/s of memory bandwidth. For comparison, Intel's Sierra Forest supports up to DDR5-6400 DRAM across 12-channels. The platform supports 2 x 96 PCIe Gen5 and 64 CXL lanes, 144 UPI (576 GB/s), and with a 576 core + 1152 MB LLC solution, you reach up to 59 TF/s that packs 5000 GB/s of raw bandwidth.

Intel's Clearwater Forest Xeon family is expected in the coming quarters, so stay tuned for a bigger launch soon.

Intel Xeon CPU Families (Preliminary):