Intel used Hot Chips to pull back the curtain on "Clearwater Forest", its next-generation E-core Xeon. The company has paired major architectural upgrades with its newest 18A process and advanced 3D Foveros packaging paired with EBIB. The chip replaces Sierra Forest and is built around the new "Darkmont" efficiency cores. Intel says Clearwater Forest will ship in a massive chiplet package using the 18A node for the compute pieces while relying on Foveros Direct 3D for stacking. The company is pitching this design as a showcase of what its foundry and packaging teams can now deliver.

Under the hood, the Darkmont E-core leans heavily on a wider, more parallel front end and a beefed-up out-of-order engine. Intel disclosed a 64 KB instruction cache per core and an expanded decoder that can handle more instructions per cycle than the previous "Crestmont" E-core design. Reorder and allocation structures have evolved, allocation units have been increased, and the out-of-order window has been enlarged to accommodate more in-flight work. Execution resources were also multiplied, with many more execution ports for integer and vector math, allowing the cores to sustain much higher parallel throughput.