Huawei's newest data center CPU, the KunPeng 930, underwent an analysis and teardown thanks to a creator named Kurnal on YouTube and BiliBili. The package is large, roughly 77.5 mm by 58.0 mm, and combines dense compute tiles manufactured at TSMC's 5 nm node with a sizable I/O die produced at SMIC on a more mature process, a possible 14 nm node. That hybrid split lets Huawei chase SRAM density and core scaling where it matters while shifting I/O and routing to a foundry that can absorb volume and ease supply pressure. Each compute tile contains forty Arm-derived cores tuned as the Taishan family, and the platform can be configured to reach a maximum of 80 cores in dual-die SKUs. The I/O die offers broad connectivity, as evidenced by teardown images that reveal a platform designed for 96 PCIe lanes.

At the component level, the KunPeng 930 shows cache and memory density have been a priority. Inside the compute tiles, there is a pair of private 2 MB L2 caches per core, with approximately 91 MB of shared L3 cache on the same die, representing a significant increase over the previous generation. DDR5 memory controllers are present on these compute tiles, and Huawei's diagrams indicate that there are 12 memory channels per chiplet, resulting in a total of 24 channels per processor. The photographed board shows sixteen DIMM sockets, which implies that not every theoretical memory channel is routed. The processor advertises up to 96 PCIe lanes, although the board only exposes about 80, reflecting routing and cost trade-offs. An SMIC-made I/O die would ease volume production but raise the need for firmware and software tuning to extract peak performance, so we are yet to see how these chips perform in server-centric benchmarks.