Marvell Technology, Inc. (NASDAQ: MRVL), a leader in data infrastructure semiconductor solutions, today announced the industry's first 2 nm 64 Gbps bi-directional die-to-die (D2D) interconnect, enabling chip designers to significantly boost the bandwidth and performance of next-generation XPUs while reducing power and silicon area. Delivering 32 Gbps of simultaneous two-way connectivity over a single wire, the interface IP—also available in 3 nm—sets a new standard for performance, power efficiency, and resiliency to meet the scaling demands of next-generation data centers.

The Marvell 64 Gbps bi-directional D2D interface offers bandwidth density over 30 Tbps/mm, more than three times the bandwidth density of UCIe at equivalent speeds, and a minimal depth configuration that reduces compute die area requirements to 15% compared to conventional implementations. The interface IP is also the industry's first in its class to feature advanced adaptive power management that automatically adjusts device activity to bursty data center traffic. This innovation reduces interface power consumption by up to 75% with normal workloads and up to 42% during peak traffic periods.