The kiloWatt era of CPUs is upon us, as AMD is preparing specialized cooling for its next-generation SP7 socket powering EPYC "Venice" . During the OCP APAC 2025 Summit in early August, AMD held a presentation dedicated entirely to system-level cooling using custom high-performance coldplates, cooling distribution units, and much more. However, an interesting tidbit is that AMD is likely planning to use CPUs with TDPs ranging from 700 to 1400 W. This marks AMD's first step into a kilowatt-level chip design, requiring kilowatt-level cooling. AMD is preparing to roll out its Zen 6 microarchitecture in 2026, with a server-focused flagship called EPYC "Venice." The new platform is expected to significantly increase core counts, utilizing full-sized Zen 6 cores and an updated I/O subsystem to target much stronger multithreaded throughput. AMD is reportedly configuring Venice to support as many as 256 CPU cores in a single package, a big leap intended to sharpen its position in dense compute environments.

Under the hood, Zen 6 CCDs are planned for TSMC's 2 nm N2 node, while the server I/O die will bring next-generation connectivity with PCIe Gen 6, doubling raw device bandwidth for GPUs, NVMe storage, and high-speed NICs. AMD has also pointed to memory bandwidth claims of up to roughly 1.6 TB/s, which could be achieved through faster DRAM clocks, expanding the memory controller to a 16-channel DDR5 layout from the current 12 channels, or supporting multichannel DIMM formats such as MR-DIMM and MCR-DIMM. Taken together, AMD says Venice will deliver approximately a 70% improvement in multithreaded performance compared to the current EPYC "Turin" family. However, all of that is shaping up to come with a significant power cost, as AMD gears up to cool these chips through customized solutions.