AMD will transition its next-generation "Zen 6" desktop Ryzen and server EPYC processors to a split-node strategy, placing CPU core complex die (CCD) on TSMC N2P 2 nm node variant and building the I/O die (IOD) on the N3P 3 nm node. At TSMC, volume ramp for the 2 nm node is around the third quarter of 2026, opening the door for limited shipments as early as late Q3 or broader availability in Q4 2026. Under the split approach, the compute chiplet will house the Zen 6 cores and a substantially larger shared L3 pool, while the IOD will continue to host memory controllers, PCIe lanes, USB, and the integrated GPU. Earlier rumors suggest that each CCD could contain 12 Zen 6 cores with support for SMT, and a shared L3 cache that may increase to roughly 48 MB per CCD compared with prior generations. Typical consumer configurations would pair up to two CCDs with a single IOD, creating chips with up to 24 cores and 48 threads, while server variants could scale further depending on packaging.

Performance expectations center on achieving double-digit IPC gains, higher sustained clock speeds, and improved power efficiency, thanks to the advanced process nodes. The choice of N3P for IOD helps AMD cut some costs for non-core logic, while the N2P compute die aims to extract greater generational gains. However, as with any new TSMC node, it will carry a premium over the N3P, so using it only for the compute side is the most viable choice. Platform compatibility remains for one more generation, with Zen 6 expected to support the existing AM5 socket. Users can upgrade CPUs without a full platform replacement. If the ramp timing holds, Zen 6 will arrive into a crowded second half of 2026 desktop window. For datacenter applications, the EPYC "Venice" generation, based on Zen 6, will utilize sIOD (server I/O die), implementing PCIe Gen 6, which provides a generational doubling in bandwidth to GPUs, SSDs, and NICs. AMD is also claiming memory bandwidth of up to 1.6 TB/s for these CPUs, so we could see some of that trickling down into consumer configurations.