NVIDIA is preparing a significant change in its chip strategy for its next-generation GPU design, codenamed "Feynman", as the first customer of TSMC's A16 process. This choice breaks NVIDIA's long-running pattern of adopting slightly older nodes to extract greater efficiency and performance gains for its datacenter accelerators. NVIDIA's biggest AI dies are enormous, at 104 billion transistors currently per each "Blackwell Ultra" die and occupying areas that are breaking reticle limits. Such a scale typically favors one or two generations old nodes to protect yield and thermal characteristics. To keep up with the compute demand, NVIDIA appears to be adapting its architectures to A16 while keeping other families like "Rubin" on refined N3P variants and paired with CoWoS-L packaging.

The most appealing aspect of the A16 node will be its backside power delivery, which separates power and signal routing to reduce losses and simplify floor planning. Implementations range from buried power rails that still use a front-side lowest metal layer to power vias that reach the rear side. TSMC's Super Power Rail concept enables power to be delivered directly to the transistor's source and drain terminals, resulting in lower resistance. Those choices affect efficiency, layout, and thermal behavior. Power demands for high-end AI accelerators are rising fast. Current flagship solutions already draw about 1,400 W in Blackwell Ultra, and next-generation Rubin designs are expected to exceed 2,300 W. Hence, node selection will be critical for the next-generation Feynman design, given its multi-gigawatt power requirement. If A16 reaches volume production on schedule, first silicon could arrive in late 2027 or early 2028.