PCI-SIG has announced a clear step forward for peripheral connectivity: PCIe 8.0 is being developed to run at 256 GT/s, which translates to about 512 GB/s in each direction and roughly 1 TB/s of simultaneous bidirectional bandwidth in a full x16 slot. Version 0.3 of the PCIe 8.0 specification has been released to member companies for review, marking the first formal draft from the working group. This draft is an early milestone on a multi-year path toward a final 1.0 release, and member feedback will shape further drafts as the consortium works to complete the standard by the targeted timeframe in 2028.

The draft reiterates several engineering priorities beyond raw speed. PCIe 8.0 will continue to use PAM4 signaling while doubling the bit rate over PCIe 7.0 and quadrupling it over PCIe 6.0, with a strong emphasis on keeping compatibility with past generations. Power efficiency and protocol optimizations for even higher rates are under active consideration, and the working group is testing new connector approaches. Optical links remain a topic of interest because they could extend reach and reduce energy use, but cost and interoperability questions will need to be resolved before they become mainstream in the PCIe ecosystem. Vendors and designers are already reviewing the draft as they plan silicon, switch, and system roadmaps that will leverage the next generation of bandwidth, particularly in high-performance computing and AI.