Alphawave Semi, a global leader in high-speed connectivity and compute silicon for the world's technology infrastructure, today announced the successful tapeout of the industry's leading 64 Gbps UCIe die-to-die (D2D) IP subsystem on TSMC's 3 nm process technology. Building on its 36 Gbps Gen 2 silicon success, this third-generation subsystem delivers a major advancement in performance and shoreline bandwidth density for the IP Ecosystem. With 64 Gbps per-lane uni-directional data rates, it enables the next generation of chiplet-based architectures for AI, XPUs, and data center systems, providing power-efficient, reliable multi-die SoC integration and seamless interoperability across the chiplet ecosystem.

As the first 64 Gbps UCIe IP subsystem implemented on TSMC's 3 nm process, this achievement positions Alphawave Semi as a leader in UCIe die-to-die connectivity technology. With enhanced 64 Gbps UCIe performance and reduced power consumption, the solution enables new applications, including optical connectivity for Co-Packaged Optics (CPO), which are essential for scalable systems and environments requiring high lane count radix. Furthermore, it expands D2D interconnect capabilities, supporting a custom memory interface that delivers very low power and latency with a unique form factor, offering eight times greater bandwidth density compared to conventional memory interfaces.