Cadence today announced major advancements in chip design automation and IP, driven by its long-standing relationship with TSMC to develop advanced design infrastructure and accelerate time to market, for AI and HPC customer applications. Cadence and TSMC have collaborated closely across the spectrum from AI-driven EDA to 3D-ICs to IP and photonics, enabling the world's most advanced semiconductors.

Cadence and TSMC have worked together on design infrastructure for advanced process nodes, including TSMC N3, N2 and A16, using Cadence Innovus Implementation System, Quantus Extraction Solution and Quantus Field Solver, Tempus Timing Solution and ECO Option, Pegasus Verification System, Liberate Characterization Portfolio, Voltus IC Power Integrity Solution, Genus Synthesis Solution, Virtuoso Studio and Spectre Simulation Platform. Cadence AI design flows for chip and 3D-IC are now available for TSMC's advanced N3, N2 and A16 process technologies, as well as for new features in TSMC 3DFabric. Additionally, Cadence is collaborating with TSMC on EDA flow development for TSMC's A14 process, with its first PDK to be released later this year. Further, several new Cadence IP are now silicon-proven and available for TSMC N3P.