According to High Yield YouTube channel, AMD is reportedly moving away from SERDES-based die-to-die links and toward a wide, parallel "sea-of-wires" routed through fan-out and RDL packaging, and the first hints of that change showed up in Strix Halo APU photos. The samples reveal a rectangular pad field where you would expect a fan-out, and the large SERDES block that used to sit at CCD edges is noticeably absent. That pattern, along with packaging choices consistent with TSMC's InFO-oS, suggests AMD is trying out dense parallel traces so fabric lanes can cross the package without being channeled into a few separate high-speed serial links. Usual serializing and deserializing data at every package boundary uses power and adds latency, thanks to clock recovery, equalization, and encoding and decoding overhead.

By moving to many short parallel wires, AMD can eliminate repeated PHY work and reduce round-trip delays, while allowing raw bandwidth to scale by adding physical lanes. The approach also frees the area that was once consumed by large SERDES blocks, which could let CCDs, memory controllers, and accelerators sit closer together with lower communication cost. There are real tradeoffs to solve, though. Packing lots of parallel traces under a die raises signal integrity, thermal, routing, and manufacturing challenges, so multi-layer RDL design and close co-engineering between die and package teams will be essential. If AMD can address those issues and carry the approach into Zen 6, we could see real per-watt and latency improvements for CPU workloads, including a faster memory IMC, thanks to lowered latency from the I/O die.