In an interview with Yahoo Finance right after the surprising OpenAI partnership announcement, AMD CEO Lisa Su confirmed that the next generation of Instinct MI450 graphics accelerators will use 2 nm process technology. "We are very excited about our MI450 generation. It has 2 nm technology, the most advanced fabrication capability," AMD CEO Lisa Su said. AMD uses TSMC's capabilities and technology, having been a loyal partner of the Taiwanese company for years. More details recently leaked from Kepler_L2 show that the TSMC N2P (2 nm) node is only used for the XCD (Accelerator Core Die), while the AID (Active Interposer Die) and MID (Media Interface Die) use the TSMC N3P process.

MI450 is set to go head-to-head with NVIDIA's Ruby generation, which uses the TSMC 3 nm (N3P) process. AMD said MI450 will deliver similar FP4/FP8 performance but with 1.5x more memory and bandwidth. AMD will use the TSMC 2 nm node for both Instinct MI450 and the next-generation EPYC "Venice" server processors, with the accelerators expected to be larger and much more complex to make. As we reported earlier, credible rumors suggest AMD will use Samsung HBM4 memory chips for the Instinct MI450 accelerators—though AMD hasn't confirmed this yet. With the year ending and CES 2026 just three months away, AMD is expected to showcase the next-gen Instinct MI400 series (and possibly even the new EPYC "Venice" generation) in January.