AMD used the Open Compute Project Global Summit in San Jose to provide an update on openSIL, its initiative to replace the legacy AGESA firmware with an open silicon-initialization stack, with timelines for CPUs based on the "Zen 6" IP. Chief Firmware Architect Raj Kapoor presented the latest developments and confirmed that slides and a video of the talk are now available to the public. As part of the update, AMD released the openSIL Firmware Architecture Specification 1.0 and initial platform code for its Phoenix client SoCs, marking a shift from proof-of-concept work to wider platform availability. Kapoor also outlined a practical release schedule for future platforms. AMD reiterated that it will initially keep some platform sources under NDA until product launch, then release open-source platform code approximately one quarter after shipping.

According to this schedule, AMD plans to publish the "Venice" 6th Gen EPYC openSIL sources in 2026, suggesting a Venice product launch by Q3 in 2026, and to release the "Medusa" Ryzen CPUs based on "Zen 6" sources in the first half of 2027. The openSIL is designed as a modular, three-part static library written to modern C standards, intended to integrate seamlessly with any x86 host firmware while remaining scalable for different customer needs. Beyond timelines and deliverables, AMD envisioned openSIL as an effort to enhance transparency, speed up integration for hyperscalers, and improve security through auditable code. The project will allow public pull requests, although contributions will be reviewed to protect sensitive microarchitectural IP. This balance between openness and protection was a recurring theme in the presentation, as AMD seeks to open more of its firmware for community collaboration while managing to expose just enough of core design details that drive its CPUs.