AMD has released its "Zen 6" instruction set manual to both consumers and enterprise, which includes new CPU instructions that many have been anticipating. In the latest Znver6 ISA manual, we see instructions like AVX512_BMM, AVX512_FP16, AVX_NE_CONVERT, AVX_IFMA, and AVX_VNNI_INT8, among others. This is particularly noteworthy because 16-bit AVX-512 calculations will now be possible on consumer-oriented desktop CPUs, allowing developers to efficiently accelerate applications and data paths that leverage AVX-512. One of the HPC engineers on X, @FelixCLC_ , notes that the introduction of these instructions means that the regular CPU becomes a universal base platform, fulfilling its intended role with enhanced observability.

A set of GNU compiler patches confirms this, as the new open-source enablement adds AVX512_BMM, AVX_NE_CONVERT, AVX_IFMA, AVX_VNNI_INT8, and AVX512_FP16 to GCC. These instructions are particularly interesting due to their intended use cases. AVX-512 BMM is designed for bit matrix manipulation, significantly accelerating local AI deployments. With native FP16 calculations and AVX VNNI in INT8 format on desktops, users will no longer need to rely on Intel Xeon CPUs for AVX-related development and process acceleration. This development benefits more users across the entire product family based on Zen 6. AMD is now directly competing with Intel in AVX development, meaning the difference between the two will come down to implementation strategy. There is also increasing evidence that Intel's next-generation "Nova Lake" will reintroduce AVX-512 functionality to desktops, suggesting that advanced vector and matrix acceleration is set to expand on consumer PCs.