CXL 4.0 announced
The spec was published at SuperComputing (SC) 25.
CXL Consortium has released the CXL 4.0 specification, the next step for its coherent interconnect that links CPUs, accelerators, and memory devices. CXL 4.0 is based on PCIe 7.0 and targets data center workloads such as AI, cloud, and hyperscale deployments.
Compared to CXL 3.x, the main change is link speed. CXL 3.0 and 3.1 run at 64 GT/s using PCIe 6.x. CXL 4.0 doubles this to 128 GT/s while keeping latency flat and retaining the 256 byte FLIT format introduced with CXL 3.x. The new spec also adds a native x2 link width option and support for up to four retimers, which helps build longer and more complex topologies without sacrificing signal quality.
CXL 4.0 introduces Bundled Ports, which let a host and a Type 1 or Type 2 device aggregate multiple physical ports into one logical attachment. This allows much higher bandwidth while the system still sees a single device, so the software model stays simple. The spec also improves memory reliability and serviceability with finer grained corrected error reporting, host initiated post package repair at boot, and more flexible memory sparing options that can run at boot or be deferred.
Source: CXL
Across generations, CXL keeps backward compatibility while raising speed and adding fabric features. CXL 1.1 and 2.0 use PCIe 5.0 at up to 32 GT/s and focus on basic coherent attach, with CXL 2.0 adding switching, memory pooling, and CXL IDE link encryption. CXL 3.0 and 3.1 move to PCIe 6.0, double bandwidth to 64 GT/s, introduce 256 byte FLIT mode, and add full fabric support with multi level switching, peer to peer transfers, memory sharing, and fabric attached memory.
CXL 4.0 builds on this fabric model, shifts to PCIe 7.0 at 128 GT/s, adds Bundled Ports and stronger memory maintenance features, and remains backward compatible with all earlier specs.
| CXL Specs | ||||
|---|---|---|---|---|
| VideoCardz.com | CXL 1.0 / 1.1 | CXL 2.0 | CXL 3.0 | CXL 4.0 🆕 |
| Physical layer | PCIe 5.0 | PCIe 5.0 | PCIe 6.0 | PCIe 7.0 |
| Transfer rate | 32 GT/s | 32 GT/s | 64 GT/s | 128 GT/s |
| Flow control unit length (FLIT) | 68B | 68B | 68B / 256B | 256B |
| Persistent memory support | No | Yes | Yes | Yes |
| Memory pooling | No | Yes | Yes | Yes |
| Memory sharing | No | No | Yes | Yes |
| Switching levels | None | Single level | Fabric (multi-level) | Fabric (multi-level) |
| Type 1 & 2 devices per root port | 1 | 1 | 16 | 16 |
| Type 3 devices (memory entities) | 1 | 16 | 4,095 | 4,095 |
| Authentication | No | Yes (CXL IDE) | Yes (CXL IDE) | Yes (CXL IDE / TSP) |
| Encryption | No | Yes | Yes | Yes |
| Connectivity level | Node | Rack | Rack / fabric | Rack / fabric |
| I/O | Ordered | Ordered | Unordered | Unordered |
Source: CXL
