According to one of the most reliable Intel leakers, the upcoming Intel "Nova Lake" desktop processors will carry 144 MB of bLLC cache to boost their already existing cache configuration and give Intel an equivalent to AMD's 3D V-Cache for enhanced gaming. Intel already uses bLLC in its "Clearwater Forest" server processors as a passive interposer, where local cache integrates beneath active tiles, so its inclusion in a standard gaming chip could deliver a significant performance uplift. As the new leak notes, bLLC implementation will be made on the compute tile, so it is close to the massive core cluster Intel is preparing to debut.

The 52-core top SKU is a tiled design that pairs two compute tiles with a single SoC tile. Each compute tile houses eight P-Cores based on "Coyote Cove" and 16 efficient E-Cores based on "Arctic Wolf," while the SoC tile contributes four low-power Arctic Wolf LPE-cores. That gives Nova Lake-S a 16 P-Core, 32 E-Core, and 4 LPE-Core configuration totaling 52 cores for the top SKU, with single-tile variants offering a 28-core option. Since there are two compute tiles, we have to wonder if Intel will implement a single 144 MB bLLC block for the entire dual-tile group, or if it will come as two 72 MB blocks.