Please note that this post is tagged as a rumor .
Leakers disagree on Intel Nova Lake-S bLLC plans, but at least two SKUs seem likely
Kopite7kimi is best known for NVIDIA GPU leaks. The same leaker has now shared more details on Intel’s Nova Lake-S desktop plans, this time focused on the new bLLC cache, Intel’s answer to AMD 3D V-Cache. According to his latest post, Intel has at least four desktop SKUs on the roadmap that use this extra cache layer, all targeting the LGA-1954 platform and Core Ultra 400K lineup. These parts are still described as early plans, not as a final product list.
The new claim describes two dual-compute tile designs and two single-tile designs. At the top are 2x 8+16 and 2x 8+12 layouts, with each compute tile paired with 144 MB of bLLC, for a total of 288 MB on the dual-tile parts. Below that sit 8+16 and 8+12 single tile SKUs, each with 144 MB of bLLC. That would put a possible 48 core configuration on the table, or 52 cores if you count the extra 4 low power cores, plus a large last level cache pool aimed at gaming workloads.
There are four skus with bllc.
— kopite7kimi (@kopite7kimi) November 26, 2025
8+12
8+16
(8+12)+(8+12)
(8+16)+(8+16)
Not 100% sure yet.
The power supply design of the new platform will be a challenge for motherboard manufacturers.— kopite7kimi (@kopite7kimi) November 26, 2025
Other leakers only mention two SKU configurations
This clashes with information shared earlier by leaker Jaykihn. He previously indicated that Nova Lake-S bLLC is reserved for unlocked K-series models, but only in two tile variants: 8+16 and 8+12 . When we asked him directly about dual bLLC or dual tile SKUs, he did not confirm any such plans. His comments about positioning also hint that these chips might not sit as extreme flagships, aka Ultra 9. Instead, they could end up closer to Core Ultra 5 or Core Ultra 7 tiers rather than a giant 48 core gaming halo SKU.
The naming for segmentation is not finalized, but it’s around the Ultra 5 level relative to the entire lineup.
— Jaykihn (@jaykihn0) November 25, 2025
Right now, the full picture is unclear. Kopite7kimi suggests Intel has at least evaluated four bLLC SKUs, including ambitious dual tile designs with 288 MB of cache, while Jaykihn still only stands by two single tile bLLC chips. AMD adds more pressure here, since recent rumors mention a Ryzen 9 9950X3D2 with dual X3D CCDs , which would bring stacked cache to both chiplets. Intel may still be deciding how far it wants to go with Nova Lake-S on desktop, so both four chip and two chip bLLC lineups remain possible until the company locks down its 2026 product stack.
| Intel Desktop Platforms Specs (Rumors) | ||||||
|---|---|---|---|---|---|---|
| VideoCardz.com | Codename | Socket | CPU Cores | GPU | NPU | BLLC |
| 12th Gen Core Alder Lake-S | Alder Lake-S | LGA-1700 | 16x (8P + 8E) | Xe-LP | ❌ | ❌ |
| 13th Gen Core Raptor Lake-S | Raptor Lake-S | LGA-1700 | 24x (8P + 16E) | Xe-LP | ❌ | ❌ |
| 14th Gen Core Raptor Lake-S Refresh | Raptor Lake-S Refresh | LGA-1700 | 24x (8P + 16E) | Xe-LP | ❌ | ❌ |
| Core (Ultra) 200 Arrow Lake-S | Arrow Lake-S | LGA-1851 | 24x (8P + 16E) | Xe-LPG | NPU3 | ❌ |
| Core (Ultra) 200 Arrow Lake-S Refresh | Arrow Lake-S Refresh | LGA-1851 | 24x (8P + 16E) | Xe-LPG | NPU3 | ❌ |
| Core (Ultra) 400 Nova Lake-S ⬅️ | Nova Lake-S | LGA-1954 | 52x (16P + 32E + 4 LP) | Xe3(p)-LPG | NPU6 | ✅ |
Source: Kopite7kimi , Jaykihn
