Two days ago, Jaykihn claimed that an unannounced Intel "Nova Lake-S" SKU would carry 144 MB of bLLC (Big Last Level Cache) cache . In theory, this generous supplementary provision could elevate Team Blue's placement in the gaming desktop CPU market—where AMD has enjoyed plenty of success, courtesy of their 3D V-Cache-laden offerings. Yesterday, kopite7kimi weighed in with additional insider information. Specifically, they proposed that Intel is readying four individual "unlocked" SKUs—as part of the late 2026 "Core Ultra 400" CPU family—that will feature implementations of bLLC. Experts believe that this stash of cache will be bunged onto the "Nova Lake-S" design's compute tile.

Hours later, kopite7kimi replied to a query regarding possible differing compute die configurations. They outlined the potential existence of dual-tile options, alongside expected single-tile alternatives. Rumors of a 52-core engineering sample emerged at the start of September—leveraging a dual-tile configuration, comprised of two 8+16 layouts, plus 4 low power cores. This week, experts posit that a variant could launch with 144 MB of Big Last Level Cache implemented on each tile, thus granting a total of 288 MB bLLC within that package. kopite7kimi warned that this information was not completely concrete, and threw in another quick forecast: "(I am) not 100% sure yet. The power supply design of the new platform will be a challenge for motherboard manufacturers." The other dual-tile option could make do with a lesser core count: comprised of two 8+12 tiles.