At last week's Open Innovation Platform Ecosystem Forum in Amsterdam, TSMC provided more details over its custom HBM for the HBM4 generation, according to reports from HardwareLUXX. The company's custom C-HBM4E logic die is expected to shift to the N3P node, alongside a voltage drop from 0.8 V to 0.75 V. According to TSMC's presentation, the move targets roughly 2× better power efficiency versus today's DRAM processes. Even standard HBM4 base dies will see upgrades. Instead of using a conventional DRAM process as in HBM3E, TSMC plans to manufacture HBM4 base dies on its N12 logic node, reducing operating voltage from 1.1 V to 0.8 V. The company expects this alone to provide around a 1.5× efficiency gain. For C-HBM4E specifically, the base die doesn't just move to the N3P node, it also integrates the memory controllers directly into the stack. Those blocks normally sit on the host SoC, so the PHY becomes a fully custom design as well.

Moreover, TSMC is expanding its advanced packaging lineup with updated InFO and SoW options, but CoWoS remains the company's main growth driver. After moving from 1.5× to 3.3× reticle sizes with support for eight HBM chips, CoWoS now heads toward CoWoS-L, enabling up to 12 HBM3E/HBM4 stacks for 2026 AI parts, followed by a larger A16 generation version planned for 2027. TSMC is also securing major customers for its custom HBM logic dies. Micron has selected the foundry to build the logic base die for its HBM4E parts, with volume production planned for 2027. SK Hynix is also reportedly preparing its first custom HBM4E products for the second half of next year. According to Korea Financial Times, SK Hynix will use TSMC's 12 nm process for mainstream server-grade HBM base dies, while NVIDIA 's top-end GPUs and Google's TPUs will step up to a 3 nm node.