Dai Nippon Printing Co., Ltd. (DNP) today announced the development of a nanoimprint lithography (NIL) template featuring a circuit line width of 10 nanometers (nm: 10-9 meter). The new template enables patterning for logic semiconductors equivalent to the 1.4 nm generation and meets the miniaturization needs of cutting-edge logic semiconductors used in devices such as smartphones, data centers, and NAND flash memory.

Background and Aims
In line with the shift to more sophisticated devices seen in recent years, demands have emerged for even greater miniaturization in cutting-edge semiconductors, leading to advances in Extreme Ultra-Violet (EUV) lithography-based production. EUV lithography, however, requires substantial capital investment, energy consumption, and operating costs in building production lines and the exposure process. This has fed into the pressing need to balance a reduction in manufacturing costs with a lowering in the environmental burden.